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Voice chip

TRSP(M)4040A

    TRSP(M)4040A series are 4-bits micro-controller which could play 1 channel melody or 1 channel ADPCM with PWM direct drive circuit. PWM resolution is 8/10/12 bits. They include a low cost, high performance CMOS micro-processor. The clock frequency of this up is typically 4.096 (±3%) MHz. This chip operates over a wide voltage range of 1.5V~5.5V. It contains program ROM (PROM) and data ROM (DROM) inside. 
    The program ROM is 4K/8K words and data ROM size is120K/112K bytes. The maximum working SRAM is (64+2) nibbles. It is provided with total 4 software programmable I/O Ports.
    TRSP(M)4040A General Descriptions:
        TRSP(M)4040A series are 4-bits micro-controller which could play 1 channel melody or 1 channel ADPCM with PWM direct drive circuit. PWM resolution is 8/10/12 bits. They include a low cost, high performance CMOS micro-processor. The clock frequency of this up is typically 4.096 (±3%) MHz. This chip operates over a wide voltage range of 1.5V~5.5V. It contains program ROM (PROM) and data ROM (DROM) inside. 
        The program ROM is 4K/8K words and data ROM size is120K/112K bytes. The maximum working SRAM is (64+2) nibbles. It is provided with total 4 software programmable I/O Ports.

    TRSP(M)4040A Features:
    *Operating voltage: 1.5V to 5.5V 
    *MCU Operation frequency: 2.048/4.096 MHz 
    *Memory Size 
       -Program ROM size: 4K/8K*12-bits OTP type 
       -Data ROM size: 120K/112K bytes OTP type 
       -SRAM size: 96*4 bits 
       -User register: 2*4 bits 
    *Wakeup function for power-down mode: 
       -HALT mode wakeup source: Port A can wake up from HALT mode to NORMAL mode and executing wakeup sub-routine program. 
    *4 input/output pins: Port A can be defined as input or output port bit by bit. 
    *Three reset condition: 
       -Low voltage reset. (LVR = 1.45V) 
       -Power on reset. 
       -Watch dog timer overflow. 
    *One internal interrupt sources: 
       -PWM interrupt. 
    *WDT 
       -Watch dog timer, can enabled/disabled by option. 
       -WDT period is 256*256*16/Fsys. (WDT period is 0.13 sec for system clock=2.048MHz) 
    *Audio output: 
       -Support PWM mode. 
       -Support 8/10/12 bits. 
    *Support option set for pull down resistor 1M, 50K Ohm, low voltage reset…etc. 
    *Oscillator fuse option ±3%, temperature & voltage compensation. 
    *Support security option (1 bit) for read inhibition. 
    *Support 16-levels LVD function.

    TRSP(M)4040A Package:
    TRSP(M)4040A provides SOP8
    TRSP(M)4040A Block Diagram:
    TRSP(M)4040A The Application Circuit:
    Notice: C1 : 10 uF ~ 100 uF(depends on applications), C2:0.1 uF
    Please submit your basic information and send an email Sales@ChipSourceTek.com , or call us at 13823761625 (the same number as wechat), and we will contact you as soon as possible!

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