Comparison of synchronous reset and asynchronous reset

2. Advantages and disadvantages of each:

1. In general, there are about three advantages of synchronous reset:

a, conducive to the simulation of the simulator.

b, can make the designed system become 100% synchronous timing circuit, which is greatly conducive to timing analysis, and the integrated fmax is generally higher.

c, because it is only effective when the clock effective level arrives, it can filter out burrs higher than the clock frequency. He also has many shortcomings, mainly the following:

A. The effective duration of the reset signal must be greater than the clock cycle in order to be truly recognized by the system and complete the reset task. Also consider factors such as clk skew, combined logical path delay, reset delay, etc.

B. Because most of the DFF in the target library of the logic device has only an asynchronous reset port, if the synchronous reset is used, the synthesizer will insert the combined logic in the data input port of the register, which will consume more logical resources.

2, for asynchronous reset, there are three advantages, all of which are corresponding

A. Most of the dff of the target device library has an asynchronous reset port, so using asynchronous reset can save resources.

B. The design is relatively simple.

c, the asynchronous reset signal is easy to identify, and you can easily use the global reset port GSR of FPGA.

Cons:

a, in the reset signal release (release) is prone to problems. Specifically, if the reset release is precisely near the effective edge of the clock, it is easy to make the register output metastable, resulting in metastability.

B. The reset signal is susceptible to burrs.

Iii. Summary:

Therefore, it is generally recommended to use asynchronous reset and synchronous release, and the reset signal is low and effective. So you can have the best of both worlds.

2: indicates the recommended reset mode

The recommended reset method is described above: "asynchronous reset, synchronous release". This combines the advantages of both sides and well overcomes the disadvantages of asynchronous reset (because the problem of asynchronous reset mainly occurs when the reset signal is released, for specific reasons seen above).

In fact, it is not difficult to do, I recommend a way I often use it: that is, add a so-called "reset synchronizer" after the asynchronous reset key, so that you can synchronize the asynchronous reset signal, and then use the processed reset signal to act on the system, you can ensure that it is relatively stable. The reset sychronizer Verilog code is as follows:

module Reset_Synchronizer

(output reg rst_n,

input  clk, asyncrst_n);

reg rff1;

always @ (posedge clk , negedge asyncrst_n) begin

if (! asyncrst_n) {rst_n,rff1} <= 2‘b0;

else {rst_n,rff1} <= {rff1,1‘b1};

end

endmodule

As you can see, this is a dff, the asynchronous reset signal is directly connected to its asynchronous reset port (low effective), and the data input rff1 is always high ‘1‘. If the asynchronous reset signal is valid, the trigger is reset, the output is low, and the successor system is reset. However, because this is a clock edge trigger, when the reset signal is released, the output of the trigger has to delay one clock cycle to restore to ‘1‘, so that the release of the reset signal is synchronized with the clock edge. In addition, there is a more direct method, which is to add a D trigger directly after the asynchronous reset signal, and then use the output of the D trigger as the reset signal of the post-stage system, which can also achieve the same effect. I won‘t say any more here.

3: The processing method of reset in multi-clock system)

This is a very practical problem, because in larger systems, one clock driver signal is obviously not enough to meet the requirements, and must use multiple homologous clocks (of course, can also be non-homologous) to drive different parts of the system according to the requirements of the system. So in such a multi-clock system, how to set the reset key? Its stability is directly related to the stability of the entire system, so pay special attention to it (in my opinion, the position of the reset signal in the synchronous timing system is as important as the clock signal). Here are the specific handling methods, of course, the principle followed should still be the above "asynchronous reset, synchronous release" :

1.non-coordinated reset removal: As the name implies, it refers to the reset signal of multiple homologous clock domains in the same system, which is driven by independent "reset synchronizer". When the asynchronous reset signal is effective, each clock domain is reset at the same time, but the reset release time is determined by the respective drive clock, which is to say: the clock is released first for the fast clock, and the clock is released after the slow clock, but there is no relationship between the reset signals.

2.sequence coordinated reset removal: This is relative to the above method, that is to say, the reset signals of each clock domain are related to each other, and although each part of the system is reset at the same time, they are released in stages. The scheduling sequence depends on the cascading mode of each reset synchronizer. You can reset the front stage first, then the back stage, or vice versa. Anyway, the method is flexible and needs to be determined according to actual needs. Due to the problem of uploading pictures, I can only use the program to express, everyone together or see, haha

Example: three-stage reset system, the clocks in the system are 1M,2M,11M:

First level Reset_Sychronizer program:

module Reset_Synchronizer

(output reg rst_n,

input  clk, asyncrst_n);

reg rff1;

always @ (posedge clk , negedge asyncrst_n)

begin

if (! asyncrst_n) {rst_n,rff1} <= 2‘b0;

else {rst_n,rff1} <= {rff1,1‘b1};

end

endmodule

Level 2,3 Reset_Sychronizer program:

module Reset_Synchronizer2

(output reg rst_n,

input  clk, asyncrst_n,d);

reg rff1;

always @ (posedge clk , negedge asyncrst_n) begin

if (! asyncrst_n) {rst_n,rff1} <= 2‘b0;

else {rst_n,rff1} <= {rff1,d};

end

endmodule

Source program of the top-level module:

include "Reset_Synchronizer.v"

include "Reset_Synchronizer2.v"

module AsynRstTree_Trans

( input  Clk1M,Clk2M,Clk11M,SysRst_n,

output SysRst1M_n,SysRst2M_n,SysRst11M_n

);

Reset_Synchronizer Rst1M(.clk(Clk1M),. asyncrst_n(SysRst_n),.rst_n(SysRst1M_n));

Reset_Synchronizer2Rst2M(.clk(Clk2M),.d(SysRst1M_n),. asyncrst_n(SysRst_n),.rst_n(SysRst2M_n));

Reset_Synchronizer2Rst11M(.clk(Clk11M),.d(SysRst2M_n),. asyncrst_n(SysRst_n),.rst_n(SysRst11M_n));

endmodule