Analysis of some common problems in digital circuit design
Time:2023-02-16
Views:1324
Abstract: With the help of the design circuit of a two-way timer, this paper analyzes the common problems in three aspects of digital circuit design in detail in the form of examples, and puts forward some opinions, that is, for the control design, based on the analysis of its essential requirements, the key to solving the problem is to select the appropriate input control signal and correctly list the truth table or status table, In terms of timing, the characteristics of synchronization and asynchrony are compared, and it is pointed out that synchronous "frequency division" and asynchronous "cascade" can be used to complete the design. In terms of pins, several special pins in general chips are analyzed and the concepts that are not easy to understand are accurately described.
The 21st century is the information age, which is also called the digital age, and its supporting foundation is the digital circuit. Therefore, the current digital circuit has been widely used in various fields. Digital circuit is a circuit that realizes logic functions and carries out various digital operations. The design of digital circuit mainly includes: analysis requirements, determination of scheme, design of circuit, assembly and commissioning, etc. In each design step, we will inevitably encounter various problems. The following is to analyze some common problems in digital circuit design.
1 FAQ analysis
With the help of the two-way (plus minus) timer designed by students, as shown in Figure 1, this paper discusses three common problems in circuit design.
The circuit shown in Figure 1 can realize 0~30 s bidirectional (plus or minus) timing, which is the advantage of this circuit, because most common circuits are unidirectional timing circuits at present, and Figure 2 shows its simulation waveform. The circuit consists of a second pulse generator, a counter, a decoding and display circuit, and various control circuits. Specifically, a NE555 working in the multi-harmonic oscillation mode generates a 1 Hz clock CP, which excites two asynchronous sequential 74LS192 to start counting through the clock control circuit, outputs the counting to two 74LS48 for decoding, and finally completes the timing display by two seven-segment nixie tubes. The control part mainly includes: switch K1 and RS latch to complete the timing start and pause Linkage switches K2-K5 and monostable circuits complete the addition and subtraction of counting clock switching and corresponding initial value setting, LED and limit value feedback control circuits complete alarm, clock CP control, etc.
1.1 Control
In the design, the circuit performance index requirements are analyzed first, and then the design scheme (or principle block diagram) is established. Generally, it is easy to build the main functional modules by selecting appropriate functional devices on this basis. However, how to correctly "connect" all functional modules and finally realize all circuit functions is often a headache in the actual design, and I believe many designers have the same feeling.
Here, this part is called the design problem of control. The essential requirement is: logically, some signals (called control signals) need to be used to determine one or some signals (controlled signals). The solution is to design this part as a simple logic circuit (combinational logic or sequential logic). Therefore, the key step is to select the appropriate input control signal and correctly list the truth table (for combinational logic circuits) or state table (for sequential logic circuits).
In practice, it usually belongs to combination logic, that is, the output state at this time is determined by the input state at this time, reflecting the connotation of "real-time" control. This paper discusses the control of combinational logic, and takes the alarm control and clock control in the aforementioned circuit as an example.
1) Alarm control
In the circuit shown in Figure 1, the LED alarm function is required to be realized when the forward timing is up to 30 s or the reverse timing is down to 00 s.
First of all, it is necessary to select the appropriate input control signal. From the perspective of feedback control, generally select two 74LS192 counting output terminals (QDQCQBQA). For one-way counting alarm control, it can. However, for bidirectional counting, because the counting output of the two 74LS192 is "0000001" and "00000000" corresponding to the limit values of 30 s and 00 s of the plus and minus timing, it can be seen that the QBQA of only the high-order (ten-bit) 74LS192 is different in the two states. After careful analysis, it is impossible to achieve alarm control only with the output of the two 74LS192, and it is necessary to find the signals related to these two limit states, It is not difficult to find that the initial value input (DCB A) of the two 74LS192 can help us solve the problem. Finally, the counting output terminal QBQA and the initial value input terminal A of the high-bit (10-bit) chip 74LS192 are selected as the input control signals.
Secondly, correctly list the truth table, as shown in Table 1. Because the LED is connected by common cathode, the alarm control output is low and effective, indicated by.
Finally, according to Table 1, the logical expression is
The alarm control circuit designed by formula (1) is shown in the dashed box in Figure 1.
2) Clock control
Clock control is generally involved in sequential logic circuit design. The timing start/pause/end functions in the circuit shown in Figure 1 are realized by controlling the opening and closing of the clock CP. In the figure, the output LRS latch of the basic RS latch realizes timing start/pause the output of the above alarm control realizes timing end. Therefore, the LRS latch, and clock CP are selected as the input control signals, and the truth table is listed as shown in Table 2, where the output is represented by L clock control. It may be difficult to deal with the input signals of high and low levels such as clock CP when listing the truth table. The method is to list both high and low levels.
Clock control is generally involved in sequential logic circuit design. The timing start/pause/end functions in the circuit shown in Figure 1 are realized by controlling the opening and closing of the clock CP. In the figure, the output LRS latch of the basic RS latch realizes timing start/pause the output of the above alarm control realizes timing end. Therefore, the LRS latch, and clock CP are selected as the input control signals, and the truth table is listed as shown in Table 2, where the output is represented by L clock control. It may be difficult to deal with the input signals of high and low levels such as clock CP when listing the truth table. The method is to list both high and low levels.
The logical expression can be obtained from Table 2:
L clock control=IRS latch · I alarm control · CP (2)
The clock control circuit designed according to formula (2) is shown in the dashed part in Figure 1.
Finally, we emphasize the above two examples: the example of alarm control is to introduce that the input control signal can select (from) any helpful signal, and the example of clock control is to introduce the processing of similar CP signals when the truth table is listed.
1.2 Timing
In the design of digital circuits, it is often necessary to make a choice of timing: synchronous or asynchronous? Comparing the two, the circuit structure of asynchronous is simpler than that of synchronous, but the delay of synchronization is smaller, faster and easier to control. In the circuit design, which timing to use can be considered comprehensively. Of course, from the perspective of convenient control, synchronization is generally used.
The circuit shown in Figure 1 adopts asynchronous timing, and the connection between the two 74LS192 chips is relatively simple. A similar "cascade" method is adopted, that is, the carry and borrow output of the low bit (one bit) chip is directly used as the clock input of the high bit (ten bit) chip. For example, the burr phenomenon is often observed in the software simulation of asynchronous circuits, which is due to the large delay. This can be observed in the simulation waveform shown in Figure 2. In order to reduce the time delay, the circuit can also be changed to synchronous timing, which can be realized by "frequency division" method, that is, the NE555 generates a 1 Hz clock signal and sends it to the low bit chip (10 bits), and the NE555 generates a 1 Hz clock signal and sends it to the high bit chip (10 bits). Of course, other related control circuits also need to be modified accordingly.
Whether it is asynchronous "cascade" or synchronous "frequency division", carefully analyze that both are doing the same "work": that is, they are dealing with problems similar to "decimal". As shown in Figure 1, the low-order chip and high-order chip in the circuit are "decimal".
1.3 Pin
Only with a correct understanding of IC pins can we use IC to complete circuit design. Here are some special pins.
1) "High/low effective" pin
"High/low effective" refers to the execution of a specified action or function when the pin is high/low. For example, the 14th pin (CLR) of 74LS192 is "highly effective", that is, when the pin is at high level, perform the zeroing action (function); The 11th pin is "low effective", that is, when the pin is low, it performs preset number actions or functions.
2) "Sync" pin
"Synchronization" means that when the pin is at the effective level, the specified action or function cannot be performed immediately, but can only be performed when the effective edge of the clock comes, that is, it must be synchronized with the effective edge of the clock.
For example, the 9th pin of 74LS161, another commonly used counter, is the "synchronization" pin. When it is at the low effective level, it must wait until the effective rising edge of the clock before performing the preset number action or function.
3) "Asynchronous" pin
"Asynchronous" means that once the pin is at the effective level, it does not need to wait for the effective edge of the clock CP to execute the specified action or function immediately, and it can be asynchronous without synchronizing with the effective edge of the clock CP.
For example, the 14th pin (CLR) and the 11th pin of 74LS192 are both "asynchronous" pins. Once they are at their effective level, they will immediately perform the actions or functions of clearing and presetting.
2 Conclusion
Many problems are often encountered in the design of digital circuits. In this paper, with the help of a 0~30s bidirectional (plus or minus) timer circuit, the common problems in control, timing, pins and other aspects are analyzed in the form of example solutions.
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