Influence of Integrated Circuits on EMI Design

    IC packaging usually includes a silicon chip, a small internal PCB, and a bonding pad. The silicon based chip is installed on a small 64PCB, and the connection between the silicon based chip and the bonding pad is realized through binding lines. In some packages, it can also be realized to directly connect the small PCB to realize the connection between the signal and power on the silicon based chip and the corresponding pins on the sink package, so that the external extension of the signal and power nodes on the silicon based chip is realized. Therefore, the transmission path of the power supply and signal of the sink includes the stuffing chip, the connection with the small PCB, the PCB routing, and the input and output pins of the sink package. The control of capacitance and home inductance (corresponding to electric field and magnetic field) largely depends on the design of the entire transmission path. Some design features will directly affect the capacitance and inductance of the entire IC chip package.

    First, look at the connection mode between the silicon chip and the internal small circuit board. Many sink chips use binding wires to connect the silicon chip to the internal small circuit board, which is a very thin 6t wire between the silicon chip and the internal small circuit board. This technology is widely used because the thermal expansion coefficient (CU) of the silicon chip and the internal small circuit board are similar. The chip itself is a silicon based device, and its thermal expansion coefficient is significantly different from that of typical PCB materials (such as epoxy resin). For example, if the electrical connection point of the silicon based chip is directly installed on the internal small PCB, after a relatively short period of time, the change of the internal temperature of the IC package will cause thermal expansion and cold contraction, and the connection in this way will become invalid due to fracture. The binding wire is a lead wire mode suitable for this special environment, which can withstand bending deformation under heavy load without being easy to break

    The problem with binding wire is that the increase of current loop area of each signal or power line will lead to the increase of inductance value. The excellent design to obtain low inductance value is to realize the direct connection between the silicon chip and the internal PCB, that is, the connection point of the silicon chip is directly connected to the bonding pad of the PCB. This requires the use of a special PCB based material, which should have a very low coefficient of thermal expansion. The selection of this material will lead to an increase in the overall cost of the sink chip, so chips using this process technology are not common. However, as long as the IC that directly connects the silicon chip with the carrier PCB exists and is feasible in the design scheme, such IC devices are a better choice.

    In general, in sink packaging design, reducing inductance and increasing capacitance between signal and corresponding loop or between power supply and ground are the primary considerations in the process of selecting integrated circuit chips. For example, small pitch surface mount and large pitch surface mount: compared with the process, the sink chip packaged by small pitch surface mount process should be preferred, and the IC chips packaged by these two types of surface mount processes are better than those packaged by via lead types. The sink chip of BGA package has the lowest lead inductance compared with any common package type. From the point of view of capacitance and inductance control, small packages and finer spacing usually represent an improvement in performance.

    An important feature of lead structure design is pin assignment. Since the value of inductance and capacitance depends on the proximity between signal or power supply and return path, enough return paths should be considered.

    Power pin and ground pin shall be distributed in pairs. Each power pin shall have corresponding ground pin adjacent to each other, and multiple power pin and ground pin pairs shall be distributed in this lead structure. These two features will greatly reduce the loop inductance between the power supply and the ground, help reduce the voltage transient on the power bus, and thus reduce the EAdI. Due to customary reasons, many foreign chips on the market do not fully follow the above design rules, but IC designers and manufacturers have a deep understanding of the advantages of this design method, so IC manufacturers pay more attention to power connection when designing and releasing new IC chips.

    Ideally, each signal pin needs to be assigned an adjacent signal return pin (such as a ground pin). This is not the case. Many IC manufacturers adopt other compromise methods. In BGA packaging, an effective design method is to set a signal return pin in the center of each group of eight signal pins. In this pin arrangement, the distance between each signal and the signal return path is only one pin. However, for square flat pack (QFP) or other gull wing (Gullw cut g) type ICs, it is unrealistic to place a signal return path in the center of the signal group. Even so, it must be ensured that a signal return pin is placed every 4 to 6 pins. It should be noted that different sink process technologies may use different signal return voltages. Some ICs use ground pins (such as TIL devices) as the return path of signals, while others use power pins (such as most ECI devices) as the return path of signals, while others use both power pins and ground pins (such as most CMoS devices) as the return path of signals. Therefore, the design engineer must be familiar with the IC chip logic series used in the design and understand their related work.

    The reasonable distribution of power and ground pins in IC chip can not only reduce EMI, but also greatly improve the ground bounce effect. When the device driving the transmission line attempts to pull down the transmission line to the logic low, the ground bounce reflection still maintains the transmission line above the logic low closed value level, and the ground bounce reflection may cause circuit failure or failure.

    Another important issue in IC packaging needs attention is the design of the internal PCB of the chip. The internal PCB is usually the largest component of the IC packaging. If strict control of capacitance and inductance can be achieved in the design of the internal PCB, the overall EMI performance of the system will be greatly improved. If this is a two-layer PCB, at least one side of the PCB is required to be a continuous ground plane layer, and the other side of the PCB is a wiring layer for power supply and signal. It is more ideal to have four layers of PCB board, the middle two layers are power supply and ground plane layers, and the outer two layers are used as signal wiring layers. Because the PCB inside the sink package is usually very thin, the design of the four layer board structure will lead to two wiring layers with high capacitance and low inductance, which is particularly suitable for power distribution and the input and output signals that need to be strictly controlled in and out of the package. The low impedance plane layer can greatly reduce the voltage transient of the power bus, thus greatly improving the EMI performance. This controlled signal line is not only conducive to reducing EMI, but also plays an important role in ensuring the integrity of inbound and outbound signals.